PLL frequency translator for precision clock trees
The Renesas RC32504A000GNK#BB0 is a FemtoClock® PLL-based frequency translator that accepts HCSL, LVCMOS, LVDS, or crystal inputs and delivers up to five outputs in CML, HCSL, LVCMOS, LVDS, or LVPECL formats. It operates from a 1.71 V to 1.89 V core supply plus a 3.465 V I/O rail, and is rated over the -40°C to 85°C industrial temperature range. This part is designed for clock conditioning in networking, base-station, and FPGA-based systems where jitter cleaning and format conversion are required.
Dual frequency maximums — which one applies
The frequency maximum is listed at both 180 MHz and 1 GHz. The 1 GHz figure applies to the differential output paths (CML, LVPECL, LVDS), while the 180 MHz limit governs the LVCMOS single-ended outputs.
Supply sequencing matters
Two separate supply domains — a 1.71 V to 1.89 V core and a 3.465 V I/O rail — mean the board designer must sequence or at least ensure both are clean before the PLL locks.
Lifecycle and sourcing
It is ROHS3 compliant. No official replacement or second-source alternate is recorded — this is the current FemtoClock device for this configuration.