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Renesas Electronics 8SLVP1204ANLGI8 — Clock & Timing ICs

Renesas 8SLVP1204ANLGI8 Fanout Buffer, 2 GHz, 16-VFQFN

MPN8SLVP1204ANLGI8
End of Life

Renesas 8SLVP1204ANLGI8, Fanout Buffer (Distribution), Multiplexer, 2:4 ratio, 2 GHz max, CML/LVDS/LVPECL input, LVPECL output, 2.375V-3.63V supply, -40°C to 85°C, 16-VFQFN (3x3) exposed pad.

$6.37Ref. price · indicative, final on quote
Packaging16-VFQFN Exposed Pad
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

8SLVP1204ANLGI8 specifications
ParameterValue
TypeFanout Buffer (Distribution), Multiplexer
MountingSurface Mount
Voltage2.375V ~ 3.63V
Frequency2 GHz
Operating temperature-40°C ~ 85°C
InputCML, LVDS, LVPECL
OutputLVPECL
PackageTape & Reel (TR); Cut Tape (CT)
Case16-VFQFN Exposed Pad
Number of circuits1
Ratio - Input:Output2:4
Differential - Input:OutputYes/Yes

Product details

2 GHz fanout buffer with multiplexer — what it does on the board

The Renesas 8SLVP1204ANLGI8 is a 2:4 fanout buffer with an integrated 2:1 multiplexer on the input side, meaning you can select between two differential clock sources and distribute one clean LVPECL copy to four destinations. It handles clock rates up to 2 GHz, which covers 10GbE reference clocks, SONET/SDH line cards, and high-speed ADC/DAC sampling clocks. The input stage accepts CML, LVDS, or LVPECL levels, so it can sit behind a PLL, an oscillator, or a serializer without needing a level translator.

Package and rework — 16-VFQFN with exposed pad

Housed in a 16-VFQFN measuring 3x3 mm, the exposed pad is the thermal path and the ground return. The exposed pad needs a via-in-pad or thermal via cluster under the center land.

Renesas lists the 8SLVP1204ANLGI8 as Active and ROHS3 compliant.

Frequently asked questions

Can I use 8SLVP1204ANLGI8 with a 3.3V supply?

Yes. The supply voltage range is 2.375V to 3.63V, so a 3.3V rail is within spec. The LVPECL output swing scales with VCC, so at 3.3V the differential swing will be approximately 800 mV peak-to-peak into 50 ohms to VCC - 2V.

Can 8SLVP1204ANLGI8 accept LVDS input?

Yes. The input stage is specified for CML, LVDS, and LVPECL levels. An LVDS signal from a 100-ohm terminated source connects directly to the differential input pair with no external bias network needed.

What is the equivalent for 8SLVP1204ANLGI8?

The closest functional peer is the 8SLVP1104ANLGI, which is a 1:4 fanout buffer (no input mux) with the same LVPECL output and 2 GHz bandwidth. The 8SLVP2108ANLGI/W offers a 1:8 fanout with two buffer circuits but a different input ratio. Neither is a direct drop-in replacement — the 8SLVP1204 is the only 2:4 mux+buffer in this family.