RX65N at 120 MHz — what the peripheral set buys you
The Renesas R5F565N7AGFP#30 is a 32-bit RX65N microcontroller built around the RXv2 core running at 120 MHz, with 768 KB of Flash and 256 KB of RAM. The peripheral list — Ethernet MAC, CAN 2.0B, USB 2.0 full-speed, QSPI, and multiple SCI/SPI/I²C channels — targets designs that need a single-chip gateway between an industrial fieldbus and an IP network. The 22-channel 12-bit ADC lets one MCU sample current feedback, voltage rails, and temperature sensors in a motor-drive or servo application without an external analog mux.
768 KB of program Flash gives room for a full TCP/IP stack, a CANopen or EtherCAT slave library, and a modest application layer without external memory. The 256 KB RAM is split between the CPU local SRAM and the Ethernet buffer area; a firmware engineer should budget the DMA descriptors and packet buffers against the RAM map early in the bring-up, because the Ethernet controller can consume several tens of kilobytes in descriptor rings alone.
Package and footprint — 100-LQFP
The 100-LQFP (14x14 mm body) with 0.5 mm pitch is a standard two-layer-routable footprint. 78 general-purpose I/O are available; the remaining pins are taken by power, ground, and the oscillator. The supplier device package is a 100-LFQFP — same footprint, same land pattern. The tray shipping medium means the parts arrive in antistatic trays, not tape-and-reel, so plan for pick-and-place feeder changeover if your line is set up for embossed tape.