70 ns access time — bus timing fit
The R1LV5256ESP-7SI#B0: The 70 ns access time sets the window for the memory controller to read or write data after presenting an address. The write cycle time is also 70 ns, so read and write timing are symmetrical.
Sourcing and lifecycle
It is available through independent distribution channels and can be quoted to order against an RFQ. No official second-source or direct replacement is listed in the available records, but the 28-SOP pinout is common across many 256Kbit parallel SRAMs from other manufacturers — a functional equivalent can be qualified by comparing the timing and supply specs.
