1:12 HCSL fanout for PCIe and QPI clock trees
The 9ZXL1231AKLF is a zero-delay PLL buffer from Renesas that takes one differential clock input and delivers twelve HCSL outputs, purpose-built for Intel QPI and PCI Express reference clock distribution. With a maximum output frequency of 150 MHz, it covers the 100 MHz PCIe reference clock and the 133 MHz QPI clock — the two dominant clock domains in a server or workstation chipset.
The differential input and all twelve HCSL outputs are fully differential (Yes/Yes), so each output pair requires a 100-Ohm termination to ground near the receiver — standard PCIe routing practice.
ROHS3 compliant (no exemptions), which clears EU and California market access without a substance-restriction waiver.