PCIe clock generator with integrated PLL
The Renesas 9FGV0641AKLF is a single-circuit PCI Express (PCIe) clock generator built around an integrated PLL. It accepts either an LVDS or crystal input and produces up to seven HCSL or LVCMOS outputs at frequencies up to 100 MHz. The 1:7 fanout ratio lets one reference clock feed multiple PCIe slots, root complexes, or endpoint devices without adding external fanout buffers. The part operates from a 1.7V to 1.9V supply and is housed in a 40-lead VFQFPN with exposed pad for thermal relief.
Outputs and frequency — what 100 MHz and HCSL mean for the bus
The 100 MHz maximum output frequency is the standard PCIe reference clock rate for Gen1 and Gen2 lanes. HCSL is the differential signalling format specified by the PCIe base spec for the reference clock.
That covers office equipment, datacom switches, servers in conditioned racks, and test equipment.