Skip to main content
Renesas Electronics 9FGV0641AKILF — Discrete Semiconductors
Renesas Electronics

9FGV0641AKILF PCIe clock generator, 100 MHz, 1:7 fanout

MPN9FGV0641AKILF
End of Life

Renesas 9FGV0641AKILF PCI Express (PCIe) clock generator, PLL, 1:7 fanout, 100 MHz max, LVDS/Crystal input, HCSL/LVCMOS output, 40-VFQFPN (5x5) exposed pad, tray.

$4.15Ref. price · indicative, final on quote
9FGV0641AKILF datasheet
Packaging40-VFQFN Exposed Pad
StockContact for availability
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

9FGV0641AKILF Technical Specifications
ParameterValue
Mounting typeSurface Mount
Voltage1.7V ~ 1.9V
Frequency100MHz
Operating temperature-40°C ~ 85°C
PLLYes
InputLVDS, Crystal
OutputHCSL, LVCMOS
PackageTray
Main purposePCI Express (PCIe)
Case40-VFQFN Exposed Pad
Number of circuits1
Ratio - Input:Output1:7
Differential - Input:OutputNo/Yes

Product details

PCIe clock fanout with integrated PLL

The 9FGV0641AKILF is a PCI Express (PCIe) clock generator IC from Renesas, integrating a PLL to synthesize and distribute reference clocks for PCIe lanes. It accepts either an LVDS differential input or a crystal oscillator, and outputs up to seven copies in HCSL or LVCMOS logic levels. The 1:7 fanout ratio means a single clean clock source can feed seven PCIe endpoints or slots, reducing board-level oscillator count and simplifying the clock tree. Maximum output frequency is 100 MHz, covering PCIe Gen 1 through Gen 3 reference clock requirements.

Supply and temperature envelope

The differential input accepts LVDS or a crystal; the output can be configured for HCSL (the PCIe standard) or LVCMOS for legacy logic.

Active lifecycle and compliance

RoHS3 compliant (2011/65/EU + 2015/863), with no exemptions reported.

Frequently asked questions

What is the input and output interface of 9FGV0641AKILF?

The input accepts either an LVDS differential signal or a crystal oscillator. The output can be configured as HCSL (the standard for PCIe reference clocks) or LVCMOS, depending on the application's logic level needs.

Does 9FGV0641AKILF include a PLL?

Yes, the device integrates a PLL for clock synthesis and jitter cleaning, enabling it to generate a low-jitter PCIe reference clock from a crystal or a noisy system clock.