PCIe clock fanout with integrated PLL
The 9FGV0641AKILF is a PCI Express (PCIe) clock generator IC from Renesas, integrating a PLL to synthesize and distribute reference clocks for PCIe lanes. It accepts either an LVDS differential input or a crystal oscillator, and outputs up to seven copies in HCSL or LVCMOS logic levels. The 1:7 fanout ratio means a single clean clock source can feed seven PCIe endpoints or slots, reducing board-level oscillator count and simplifying the clock tree. Maximum output frequency is 100 MHz, covering PCIe Gen 1 through Gen 3 reference clock requirements.
Supply and temperature envelope
The differential input accepts LVDS or a crystal; the output can be configured for HCSL (the PCIe standard) or LVCMOS for legacy logic.
Active lifecycle and compliance
RoHS3 compliant (2011/65/EU + 2015/863), with no exemptions reported.