PCIe reference-clock fanout without the PLL jitter
The Renesas 9DML0451AKILFT is a 2:4 differential HCSL clock buffer designed for PCI Express reference-clock trees. It takes one or two HCSL input pairs and fans out to four HCSL output pairs at up to 200 MHz — enough for PCIe Gen1 and Gen2 root complexes and slot clocks. Because it contains no PLL, there is no loop-filter noise, no lock-time delay, and the output-to-output skew is determined only by the internal buffer matching. This makes it a fit for systems that need deterministic latency and low additive jitter, such as server motherboards, storage backplanes, and base-station timing cards.
Supply and temperature — design constraints at a glance
The supply range is 3.14 V to 3.47 V. The operating temperature range is -40°C to 85°C.
Lifecycle and compliance — active, ROHS3, no LTB notice
The 9DML0451AKILFT carries an Active product status and is ROHS3 compliant.
