PLL clock buffer for PCIe reference-clock distribution
The Renesas 9DBV0441AKLF is a 1:4 PLL-based clock buffer designed to distribute HCSL reference clocks for Ethernet and PCI Express (PCIe) interfaces. It accepts one HCSL input and delivers four HCSL outputs with integrated PLL cleaning, so the output jitter is lower than the input — useful when a noisy clock source needs cleaning before reaching the PCIe PHY.
137.5 MHz ceiling — Gen1/Gen2 PCIe, not Gen3
The maximum output frequency is 137.5 MHz, which covers PCIe Gen1 (100 MHz) and Gen2 (100 MHz) reference clocks, plus standard Ethernet frequencies. It does not reach the 400 MHz range needed for PCIe Gen3 or higher-speed serial links — for those, look at the 9ZXL0851EKKLF (400 MHz, 1:8 fanout, industrial temp) or the 9DB803DFLFT (400 MHz, 1:8, 3.135 V supply). The 9DBV0441AKLF is the right fit for 100 MHz PCIe clock trees in server motherboards, switches, and storage controllers that stay within the commercial temperature band.
Active, RoHS3, surface-mount QFN
Supply and temperature — server-room only
The supply voltage tolerance (1.7 V to 1.9 V) means the part can share a 1.8 V rail with DDR memory or the core supply of an FPGA or switch ASIC, simplifying the power tree.