PCIe and QPI clock distribution without PLL phase noise
The Renesas 9DBL411BKILF is a 1:4 differential fanout buffer designed for Intel QPI and PCI Express (PCIe) reference clock trees. It accepts an HCSL input and delivers four LP-HCSL outputs with a 1:4 fanout ratio, all without an internal PLL — meaning the output phase noise is set entirely by the source oscillator, with no PLL loop-bandwidth peaking or jitter accumulation from the buffer itself. Maximum frequency is 150 MHz. Differential input and output paths are fully differential (Yes/Yes). Supply range is 3V to 3.6V, and the operating temperature spans -40°C to 85°C, making it suitable for industrial and telecom environments where ambient temperature swings are a given.
Lifecycle and sourcing
The 9DBL411BKILF carries an Active product status and is ROHS3 compliant. For new designs or BOM maintenance, the part is available through independent distribution and can be quoted to order — no lead-time surprises from a phase-out.
Why no PLL matters for your clock tree
A PLL-based clock buffer introduces its own jitter from the VCO and loop filter. The 9DBL411BKILF has no PLL, so the output jitter is simply the input jitter plus the buffer's additive phase noise — typically well under 1 ps RMS for a clean HCSL source. If your ADC or SerDes is sensitive to deterministic jitter from PLL spurs, this buffer keeps the clock clean.