PLL-based PCIe clock fanout — 1:8 HCSL distribution
The 9DB833AGLF is a PLL-based zero-delay buffer designed to fan out a single HCSL (High-Speed Current Steering Logic) input to eight HCSL outputs, with a maximum frequency of 166 MHz, purpose-built for PCI Express (PCIe) reference clock trees. The integrated PLL cleans up jitter on the incoming clock and aligns the output edges to the input with near-zero propagation delay — critical for meeting the PCIe Gen1/Gen2/Gen3 reference clock jitter specifications without adding a separate jitter cleaner.
Supply, package, and temperature grade
Housed in a 48-TFSOP (0.240", 6.10 mm width) package, also described as a 48-TSSOP supplier device package — a fine-pitch surface-mount footprint that routes the eight HCSL outputs and the single HCSL input on a standard PCB without requiring blind vias.