PCIe clock distribution with integrated PLL
The Renesas 9DB803DGLF is a 1:8 differential clock buffer for PCI Express reference-clock trees, with an integrated PLL that cleans jitter from the incoming HCSL signal before fanning it out to eight HCSL outputs. It handles the 100 MHz reference clocks used across PCIe Gen1 through Gen3 base rates, with a 400 MHz maximum frequency ceiling that also covers higher-speed serial links needing a clean differential source. The single PLL means this is a zero-delay buffer — the outputs are phase-aligned to the input, which matters when multiple PCIe slots or endpoints share a common clock domain and the layout skew budget is tight. The 1:8 ratio covers a typical desktop or server motherboard's slot cluster from one device, reducing BOM count versus cascading smaller fanout parts.
Supply and temperature — server-room fit only
The 3.135 V to 3.465 V supply range matches the standard 3.3 V PCIe clock rail with margin for ripple.
Package and mounting — 48-TSSOP with tube delivery
Housed in a 48-TFSOP (0.240", 6.10 mm width) package, also referred to as 48-TSSOP, surface-mount only. The supplier device package is 48-TSSOP. This is a fine-pitch SSOP-style body — standard reflow profiles for TSSOP apply.
Lifecycle — active, no end-of-life pressure
Renesas lists the 9DB803DGLF as Active (current production). ROHS3 compliant.