PLL-based zero-delay buffer for PCIe clock trees
The Renesas 9DB633AGLFT is a PLL-based zero-delay clock fanout buffer for PCI Express. It takes a single differential clock input and delivers six HCSL outputs, each running up to 110 MHz, with a 1:6 input-to-output ratio.
Supply and temperature — fit for controlled indoor environments
Operating from a 3.135 V to 3.465 V supply, the 9DB633AGLFT aligns with standard PCIe power rails. The commercial temperature grade (0°C to 70°C) limits deployment to controlled indoor equipment.
Package and footprint
Housed in a 28-TSSOP package (4.40 mm body width), the 9DB633AGLFT uses a standard surface-mount footprint common to many Renesas clock buffers.
Lifecycle and sourcing
The 9DB633AGLFT is listed as Active with ROHS3 compliance. There is no last-time-buy notice or obsolescence risk for new designs.
