Renesas 9DB633AGLFT, PLL Clock Fanout/Buffer, Zero Delay, 1:6 HCSL Outputs, 110 MHz, 3.135V–3.465V, 28-TSSOP, Commercial Temp.
| Parameter | Value |
|---|---|
| Mounting | Surface Mount |
| Supply voltage | 3.135V ~ 3.465V |
| Frequency - max | 110MHz |
| Operating temperature | 0°C ~ 70°C |
| PLL | Yes |
| Input | Clock |
| Output | HCSL |
| Package | Tape & Reel (TR); Cut Tape (CT) |
| Main purpose | PCI Express (PCIe) |
| Case | 28-TSSOP (0.173\", 4.40mm Width) |
| Number of circuits | 1 |
| Ratio - Input:Output | 1:6 |
| Differential - Input:Output | Yes/Yes |
The Renesas 9DB633AGLFT is a PLL-based zero-delay clock fanout buffer for PCI Express. It takes a single differential clock input and delivers six HCSL outputs, each running up to 110 MHz, with a 1:6 input-to-output ratio.
Operating from a 3.135 V to 3.465 V supply, the 9DB633AGLFT aligns with standard PCIe power rails.
No. The 9DB633AGLFT is listed as Active with no end-of-life notice. It is suitable for production BOMs and new designs.
There is no direct replacement from Renesas listed as a successor. For a higher-frequency PLL-based HCSL fanout with 1:8 ratio and industrial temperature range, consider the 9ZXL0851EKKLF (400 MHz, -40°C to 85°C). For a non-PLL LP-HCSL fanout at 150 MHz, the 9DBL411BGLFT is an alternative but lacks the zero-delay PLL.
The 9DB633AGLFT runs at 110 MHz max, which covers the 100 MHz PCIe reference clock frequency. However, PCIe Gen4 imposes tighter phase-jitter specifications (typically <0.5 ps RMS) that this part may not meet. Verify the jitter performance against your Gen4 controller requirements before specifying.