Renesas Electronics
Renesas 9DB403DFLF PCI Express (PCIe) clock buffer, PLL Yes, Input HCSL, Output HCSL LVDS, 1:4 fanout, 400 MHz max, 3.135V-3.465V supply, 0°C to 70°C, 28-SSOP, Surface Mount, Tube.
MOQ 1 · Tube · RoHS · EIA-481 · DAP/DDP · T/T
| Parameter / Attribute | Specification / Value |
|---|---|
| Mounting | Surface Mount |
| Supply voltage | 3.135V ~ 3.465V |
| Frequency - max | 400MHz |
| Operating temperature | 0°C ~ 70°C |
| PLL | Yes |
| Input | HCSL |
| Output | HCSL, LVDS |
| Package | Tube |
| Main purpose | PCI Express (PCIe) |
| Case | 28-SSOP (0.209\", 5.30mm Width) |
| Number of circuits | 1 |
| Ratio - Input:Output | 1:4 |
| Differential - Input:Output | Yes/Yes |
The 1:4 ratio lets a single reference clock source drive up to four PCIe slots, root complexes, or switch endpoints without an external fanout tree. Outputs are individually selectable between HCSL and LVDS, which simplifies BOM consolidation when mixing PCIe and non-PCIe differential receivers on the same board. The differential input and all outputs are fully differential (Yes/Yes), so no single-ended termination is needed on the clock lanes.
