PCIe reference clock fanout — 1:2 HCSL, PLL cleaned
The Renesas 9DB233AGILFT is a PLL-based zero-delay clock fanout buffer for PCI Express (PCIe) reference clock distribution. It takes one differential clock input and delivers two HCSL outputs.
Supply and package
The 20-TSSOP package (4.40 mm wide) is a common footprint for PCIe clock buffers; verify the pinout against your PCB layout before tape-out. Surface-mount only.
ROHS3 compliant, covering the full restricted-substances list beyond the original six. No lead, mercury, cadmium, or phthalates; simplifies EU and global compliance paperwork.
