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Renesas Electronics 9DB106BGLFT — DC-DC Power Modules

9DB106BGLFT PCIe Clock Buffer, 105 MHz, 1:6 HCSL, 28-TSSOP

MPN9DB106BGLFT
End of Life

Renesas 9DB106BGLFT PCI Express (PCIe) clock buffer, PLL Yes, input Clock, output HCSL, 1:6 ratio, 105 MHz max, 3.135V–3.465V supply, 0°C to 70°C, 28-TSSOP surface mount.

$4.95Ref. price · indicative, final on quote
Renesas Electronics 9DB106BGLFT datasheet (PDF)
Packaging28-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

9DB106BGLFT specifications
ParameterValue
MountingSurface Mount
Voltage3.135V ~ 3.465V
Frequency105MHz
Operating temperature0°C ~ 70°C
PLLYes
InputClock
OutputHCSL
PackageTape & Reel (TR); Cut Tape (CT)
Main purposePCI Express (PCIe)
Case28-TSSOP (0.173\", 4.40mm Width)
Number of circuits1
Ratio - Input:Output1:6
Differential - Input:OutputYes/Yes

Product details

What this PCIe clock buffer does

The Renesas 9DB106BGLFT is a zero-delay PLL buffer designed to distribute a reference clock across a PCI Express (PCIe) clock tree. It takes one differential clock input and delivers six differential HCSL outputs, each capable of driving a separate PCIe slot or endpoint. The integrated PLL cleans up jitter and aligns the output edges to the input, meeting the phase-noise and skew requirements for PCIe Gen1, Gen2, and Gen3 reference clocks.

The 1:6 fanout ratio means one input drives up to six loads — typical for a motherboard with six slots, or a riser card with multiple endpoints. If you need more outputs, the 9DB803DFLFT offers a 1:8 ratio in the same 28-TSSOP footprint.

The ROHS3 compliance is current. If you are freezing a BOM for a multi-year production run, this is a safe choice with no imminent LTB risk.

Frequently asked questions

What is the maximum frequency of 9DB106BGLFT?

The maximum frequency is 105 MHz, which covers PCIe Gen1, Gen2, and Gen3 reference clocks (100 MHz) with margin.

Does 9DB106BGLFT have differential HCSL outputs?

Yes, both the input and outputs are differential HCSL, as indicated by the Differential - Input:Output field set to Yes/Yes.

Can 9DB106BGLFT be used for PCIe Gen3 reference clocks?

Yes, the 105 MHz maximum frequency covers the 100 MHz reference clock required by PCIe Gen3 with margin. The PLL jitter cleaning and differential HCSL outputs meet Gen3 phase-noise requirements.