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Renesas Electronics 9DB106BGILF — Clock & Timing ICs

9DB106BGILF PCIe Clock Fanout Buffer, 105 MHz, 28-TSSOP

MPN9DB106BGILF
End of Life

Renesas 9DB106BGILF, PCI Express (PCIe) zero-delay clock fanout/buffer, PLL-based, 1:6 HCSL outputs, 105 MHz max, 3.135V-3.465V supply, -40°C to 85°C, 28-TSSOP, Tube, ROHS3, Active.

$5.73Ref. price · indicative, final on quote
Renesas Electronics 9DB106BGILF datasheet (PDF)
Packaging28-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

9DB106BGILF specifications
ParameterValue
MountingSurface Mount
Voltage3.135V ~ 3.465V
Frequency105MHz
Operating temperature-40°C ~ 85°C
PLLYes
InputClock
OutputHCSL
PackageTube
Main purposePCI Express (PCIe)
Case28-TSSOP (0.173\", 4.40mm Width)
Number of circuits1
Ratio - Input:Output1:6
Differential - Input:OutputYes/Yes

Product details

What this PCIe clock buffer does

The Renesas 9DB106BGILF is a PLL-based zero-delay clock fanout buffer built for PCI Express reference-clock distribution. It takes one differential clock input and delivers six HCSL outputs, all phase-aligned with low jitter. The PLL cleans up incoming jitter and compensates for board trace delay so every output edge lands in the same window — critical when you're driving multiple PCIe slots or root-complex endpoints off a single oscillator. Rated for 105 MHz maximum, this part covers PCIe Gen1, Gen2, and Gen3 reference-clock requirements. It does not reach the 400 MHz needed for Gen4 or Gen5 — if you're building a Gen4 backplane, look at the 9ZXL0851 or 9ZXL1231 family instead. The 28-TSSOP package is a surface-mount footprint.

Temperature grade and where it runs

If your board lives in a conditioned data-center rack, you could use the commercial-grade 9DB803DFLFT, but this part gives you headroom for the same BOM cost.

Frequently asked questions

Does 9DB106BGILF support PCIe Gen1/2/3/4 clock requirements?

It supports PCIe Gen1, Gen2, and Gen3 reference-clock requirements at 105 MHz maximum. It does not support Gen4 or Gen5, which require 400 MHz output. For Gen4 applications, consider the 9ZXL0851 or 9ZXL1231 families.

What are the exact specifications for 9DB106BGILF?

PLL-based zero-delay clock buffer, 1:6 differential input-to-HCSL output ratio, 105 MHz maximum frequency, 3.135 V to 3.465 V supply, -40°C to 85°C operating temperature, 28-TSSOP package, ROHS3 compliant, Active lifecycle.