PLL clock synthesizer for the Romley server clock tree
The 932SQ428AKLF is a PLL-based clock synthesizer from Renesas, designed to generate up to 13 HCSL outputs from a single crystal input. Its primary target is the Intel Romley platform — the Xeon -2600 family server chipset — where it provides the reference clocks for PCIe, QPI, and DDR3 interfaces. Maximum output frequency is 144.44 MHz, which covers the 100 MHz PCIe reference and 133.33 MHz QPI clock requirements typical of Romley designs. The differential outputs are HCSL, the standard signaling for PCIe Gen1/2/3 reference clocks.
Supply rail and temperature range for server boards
The commercial temperature grade (0°C to 70°C) suits data-center ambient conditions but is not rated for extended industrial or outdoor use. Packaged in a 48-VFQFN with exposed pad (6x6 mm), the 48-QFN footprint requires a thermal via array under the paddle for adequate heat transfer to the ground plane. Mounting is surface-mount only.
Active production — no obsolescence risk for new builds
ROHS3 compliant.
Comparing with the 9ZXL0851EKKLF — wider temperature and differential input
The 9ZXL0851EKKLF targets Intel QPI and PCIe with a 1:8 fanout and a 400 MHz maximum — higher frequency but fewer outputs.