PLL clock synthesis for S-RIO 1.3/2.0 backplanes
The 841N254BKILF is a PLL-based clock synthesizer from the FemtoClock® NG family, designed to generate the reference clocks for Serial RapidIO (S-RIO) 1.3 and 2.0 interfaces. It accepts a single-ended LVCMOS, LVTTL, or crystal input and produces up to four differential HCSL or LVDS outputs at frequencies up to 250 MHz. The 2:4 input-to-output ratio means two reference inputs can be selected to feed four clock outputs, providing fanout for multiple S-RIO ports or link partners from a single PLL.
