350 MHz fanout buffer for mixed-signal clock trees
The Renesas 83026BGI-01LFT is a 1:2 fanout buffer (distribution) that accepts differential or single-ended inputs from HCSL, LVDS, LVHSTL, LVPECL, or SSTL sources and delivers LVCMOS/LVTTL outputs. It handles clock rates up to 350 MHz, making it a fit for distributing high-speed reference clocks in networking, telecom, and data-converter systems where the input standard varies across the board. The single 3.3 V supply (3.135 V to 3.465 V) and industrial temperature range (-40°C to 85°C) suit it for base-station and industrial-control backplanes.
Input flexibility — one buffer, five signal standards
The input stage accepts HCSL, LVDS, LVHSTL, LVPECL, and SSTL levels without external level-shifting resistors. That saves board area and BOM cost when the clock source is an LVDS oscillator but the downstream logic expects LVCMOS. The differential input is converted to a single-ended LVCMOS/LVTTL output, so the part acts as a signal-format translator as well as a fanout buffer.
350 MHz — headroom for 100+ MHz clock distribution
Rated at 350 MHz maximum frequency, this buffer comfortably distributes 100 MHz, 125 MHz, or 156.25 MHz reference clocks with margin. The 1:2 fanout ratio means one input drives two output branches, each with its own LVCMOS/LVTTL drive. For designs needing more than two copies, cascade multiple 83026BGI-01LFT devices or step up to a 1:4 or 1:8 fanout buffer like the 5PB1104CMGK/W (200 MHz, 1:4, LVCMOS).
Active production, ROHS3, 8-TSSOP package
It is ROHS3 compliant, so it passes European and California regulatory requirements without an exemption.