Clock fanout with a 350 MHz ceiling and a differential input
The 83026BGI-01LF is a 1:2 fanout buffer accepting differential input standards — HCSL, LVDS, LVHSTL, LVPECL, SSTL — and producing two single-ended LVCMOS or LVTTL copies of the clock. Rated to 350 MHz maximum frequency, this part serves clock-tree fanout in systems where the source is a differential oscillator or PLL and the downstream loads are CMOS logic inputs that expect a rail-to-rail swing. The differential input to single-ended output architecture means the buffer translates a low-swing differential signal into a full-swing CMOS clock, but the 350 MHz ceiling sets the upper limit on the distributed clock rate before edge-rate degradation becomes a signal-integrity issue at the receiver.
Operates from a 3.135 V to 3.465 V supply — a tight 3.3 V nominal rail with ±5 % tolerance; the buffer's PSRR assumes the rail is clean, so a switching regulator feeding this part should be followed by a low-noise LDO or a pi-filter to keep clock jitter within budget.