What this 1:10 clock buffer does
The Renesas 74FCT3807EQGI is a single-ended fanout buffer that takes one LVTTL input and distributes it to ten CMOS or TTL outputs. The 1:10 ratio lets one oscillator or PLL output feed a ten-load clock tree without an external fanout gate.
Single-ended, not differential — a common cross-check
Both input and output are single-ended (LVTTL in, CMOS/TTL out). This is not a differential buffer — no LVPECL, LVDS, or CML support. If your design calls for differential clock distribution, the 8SLVP1104ANLGI is a 1:4 LVPECL fanout buffer that accepts CML, LVDS, and LVPECL inputs and runs at 2 GHz. The 74FCT3807EQGI is the right choice for a standard single-ended 3.3V clock tree where you need ten copies of a 166 MHz or slower signal.
The 74FCT3807EQGI comes in a 20-lead SSOP package with a 3.90 mm body width (0.154"). The supplier device package is marked as 20-QSOP, which is the same mechanical outline. Surface-mount only. The 1.27 mm pitch is standard for SSOP-20 and routes easily on two-layer boards.
Not AEC-Q100 qualified — no automotive-grade claim. For a fanout buffer in an under-hood or chassis-domain ECU, look at the 5PB1104CMGK/W which extends to 105°C and runs from 1.71V, though it is only 1:4.
ROHS3 compliant. No NRND or LTB flags. No direct second-source alternate is listed on the manufacturer cross-reference, but the 5PB1104CMGK/W covers a similar single-ended fanout function at 1:4 if your fanout requirement is smaller.