Clock fanout for single-ended trees
The Renesas 74FCT3807ASOGI is a 1:10 fanout buffer from the 74FCT series, designed to distribute a single LVTTL clock input to ten CMOS or TTL outputs.
1:10 ratio and 100 MHz ceiling
The 1:10 input-to-output ratio means one clock source drives ten loads without needing a second buffer stage. At 100 MHz the part keeps edge rates clean for most single-ended clock trees — think FPGA configuration clocks, Ethernet PHY reference clocks, or synchronous ADC sample clocks. The non-differential I/O (No/No) rules out LVPECL or LVDS fanout; this is strictly for LVTTL/CMOS rails.
20-SOIC footprint, surface-mount assembly
Housed in a 20-SOIC package (7.50 mm width), the part reflows on standard lead-free profiles. The wide-body SOIC gives good thermal contact to the PCB copper pour — useful if the buffer sits near a hot FPGA or processor. Tube shipment is the default; if your pick-and-place line feeds from tape, confirm the reel option with your distributor before committing the BOM line.
Active, no LTB watch needed
No last-time-buy notice, no end-of-life window to track.