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Renesas Electronics 74FCT16374ETPAG — Microcontrollers & Processors (MCU / MPU / DSP)

Renesas 74FCT16374ETPAG D-Type Flip-Flop, 3.7ns, 48-TSSOP

MPN74FCT16374ETPAG
End of Life

Renesas Electronics 74FCT series D-Type flip-flop, 74FCT16374ETPAG, dual 8-bit, positive edge triggered, tri-state non-inverted outputs, 48-TSSOP surface mount package.

$1.66Ref. price · indicative, final on quote
Packaging48-TFSOP (0.240", 6.10mm Width)
StockIn Stock (18)
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
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Specifications

74FCT16374ETPAG Technical Specifications
ParameterValue
TypeD-Type
Series74FCT
Output typeTri-State, Non-Inverted
Trigger typePositive Edge
Mounting typeSurface Mount
Voltage4.5V ~ 5.5V
Current - quiescent500 µA
Current - output high, low32mA, 64mA
Operating temperature-40°C ~ 85°C (TA)
PackageBulk
FunctionStandard
Case48-TFSOP (0.240\", 6.10mm Width)
Input capacitance3.5 pF
Number of elements2
Number of bits per element8
Max propagation delay @ v, max CL3.7ns @ 5V, 50pF

Product details

Dual 8-bit D-type in a 48-TSSOP footprint

The 74FCT16374ETPAG is a dual 8-bit D-type flip-flop from Renesas Electronics, part of the 74FCT logic family. Each of the two elements stores eight bits, triggered on the positive edge of the clock, with tri-state non-inverted outputs that let multiple devices share a common bus without contention. The 3.7 ns max propagation delay at 5 V and 50 pF load sets the timing budget for high-speed address or data-path pipelines. Combined with 32 mA source and 64 mA sink output drive, this part can fan out to multiple loads on a backplane without external buffers.

Supply, temperature, and package — the fit constraints

Housed in a 48-TFSOP (0.240", 6.10 mm width) package, also designated as 48-TSSOP in the supplier device package field. The 0.50 mm pitch fine-pitch TSSOP footprint is common for high-density logic; verify the PCB land pattern matches the 6.10 mm body width before committing the layout. Quiescent current is 500 µA typ, and input capacitance is 3.5 pF per pin — low enough that the clock-tree driver sees a light load even with all 16 inputs switching.

Frequently asked questions

What is the propagation delay of 74FCT16374ETPAG?

Maximum propagation delay is 3.7 ns at 5 V supply with a 50 pF load. This is the spec that governs timing closure in high-speed pipeline or bus-register applications.

What package does 74FCT16374ETPAG come in?

It is supplied in a 48-TFSOP (0.240", 6.10 mm width) surface-mount package, also referred to as 48-TSSOP. The 0.50 mm pitch requires a fine-pitch PCB land pattern.