Dual 8-bit D-type register for 5V bus applications
The 74FCT16374CTPAG from Renesas (formerly IDT) is a dual 8-bit D-type flip-flop with tri-state, non-inverted outputs, packaged in a 48-TSSOP. It is designed for high-speed 5V bus interfaces where two independent 8-bit registers are needed on a single IC, each with its own clock and output enable. Key characteristics: positive edge-triggered on each of the two elements, each element holding 8 bits, with a max propagation delay of 5.2 ns at 5V and 50 pF load. Outputs source 32 mA and sink 64 mA, providing enough drive for heavily loaded backplanes or long traces.
At 5V and 50 pF load, the propagation delay is 5.2 ns max. The 32 mA / 64 mA output drive (high / low) is asymmetric: the low-side sink is double the high-side source. That is typical for CMOS outputs that drive capacitive loads; the falling edge will be faster than the rising edge. Account for that skew when matching trace lengths on a critical clock or data strobe.
Package and footprint: 48-TSSOP
The part is supplied in a 48-TSSOP package (body 6.10 mm wide). It is a surface-mount package.
Lifecycle: active, no end-of-life concerns
The 74FCT series is a mature logic family with broad second-source availability across multiple manufacturers, though this specific suffix (CTPAG) is a Renesas/IDT ordering code.