Asynchronous FIFO with 12 ns access — bus timing fit
The IDT 7200L12SOG is a 256 x 9 asynchronous FIFO in a 28-SOIC package. Its 12 ns access time and 50 MHz data rate mean the part can sustain back-to-back read/write cycles without wait-states on a 50 MHz bus, provided the system's memory controller meets the strobe-to-data-valid window. The 9-bit width (eight data plus one parity/flag bit) is common in telecom and datacom line cards where a single-bit parity check is carried alongside the byte.
Retransmit and asynchronous operation
The asynchronous architecture uses independent read and write strobes rather than a shared clock, which simplifies glue logic when the two clock domains are unrelated. The retransmit capability lets the FIFO replay data from the first location without a full reset — useful after a CRC or parity error in a packet-based system. Depth and width expansion are supported, so multiple 7200L12SOG devices can be cascaded for larger buffers.
No last-time-buy deadline is pending.