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Renesas Electronics 71V546XS133PFGI — DC-DC Power Modules

71V546XS133PFGI Synchronous SRAM, 4.5Mbit, 133 MHz, 4.2 ns

MPN71V546XS133PFGI
End of Life

Renesas 71V546XS133PFGI, Synchronous SDR (ZBT) SRAM, 4.5Mbit (128K x 36), 133 MHz clock, 4.2 ns access, Parallel interface, 3.135V-3.465V supply, 0°C to 70°C, 100-TQFP (14x14), ROHS3.

$1.66Ref. price · indicative, final on quote
Packaging100-LQFP
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

71V546XS133PFGI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage3.135V ~ 3.465V
Frequency133 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageBulk
TechnologySRAM - Synchronous, SDR (ZBT)
Access time4.2 ns
Memory size4.5Mbit
Memory formatSRAM
Case100-LQFP
Memory organization128K x 36

Product details

The Renesas 71V546XS133PFGI is a 4.5 Mbit synchronous SRAM organized as 128K words by 36 bits. It uses a Zero Bus Turnaround (ZBT) pipeline architecture, meaning the memory can switch between read and write cycles without inserting dead cycles — a requirement for high-throughput data buffers in networking, telecom line cards, and test equipment where back-to-back transactions saturate the bus. At 133 MHz the part delivers a 4.2 ns access time from clock edge to data valid. The 100-TQFP (14x14 mm) package is a fine-pitch surface-mount footprint. The part is ROHS3 compliant.

This limits deployment to temperature-controlled environments.

Marked as Active on the lifecycle record. No NRND or last-time-buy flags.

Frequently asked questions

What is the access time of 71V546XS133PFGI?

The access time is 4.2 ns from clock edge to data valid, measured at the rated 133 MHz clock frequency. This timing drives the bus margin for the host FPGA or ASIC.

What is 71V546XS133PFGI's listed technology?

Synchronous SRAM with Zero Bus Turnaround (ZBT) and Single Data Rate (SDR) pipeline. The ZBT architecture eliminates dead cycles when switching between read and write, sustaining full bus utilization at 133 MHz.