Dual-port asynchronous SRAM — 32 Kbit, 20 ns, 5 V
The Renesas 7143LA20JG is a 32 Kbit dual-port asynchronous SRAM organised as 2K × 16 bits, with a 20 ns access time and a 4.5 V to 5.5 V supply range. It is built for applications where two independent buses — typically a DSP and a microcontroller, or two processors — need simultaneous read/write access to a shared memory block without external arbitration logic. The 16-bit word width maps directly onto a 16-bit data bus, saving byte-lane multiplexing. The part is rated for commercial temperature environments (0°C to 70°C) and comes in a 68-lead PLCC with J-leads, a surface-mount footprint common in mid-1990s through 2000s designs.
20 ns access time — bus timing margin
The 20 ns access time is the time from address valid to data valid on a read cycle. The write cycle time is also 20 ns.
Temperature grade and environment
The 0°C to 70°C operating temperature range limits this part to commercial/indoor equipment. It is not rated for industrial environments.
Package and footprint
The 68-PLCC package (24.21 × 24.21 mm body) uses J-leads. It is a surface-mount package that can be soldered directly or socketed.
Lifecycle and sourcing
The 7143LA20JG is listed as Active and ROHS3 compliant. There is no last-time-buy notice or end-of-life indication. The part is available through independent distribution and can be quoted to order. For BOM planning, there is no immediate obsolescence risk, but dual-port SRAMs are a shrinking market — most new designs migrate to dual-port RAM in FPGAs or to QDR/DDR SRAM. If the design is locked to this footprint, confirm supply annually.