1 Mbit asynchronous SRAM for 5 V bus architectures
The Renesas 71024S15TYG is a 1 Mbit asynchronous SRAM organized as 128K x 8 bits, with a parallel interface and a 15 ns access time.
The 71024S12TYG sibling has a 12 ns access time.
Housed in a 32-pin SOJ (Small Outline J-lead) package, 0.300" body width (7.62 mm), surface-mount. The SOJ footprint is standard for this density of SRAM; J-leads give a smaller footprint than SOIC but require a reflow profile that matches the lead-free (ROHS3) finish. The supplier device package is 32-SOJ — same mechanical outline. Tube shipment, so plan for tube-to-tray or tube-to-reel transfer if your pick-and-place feeds from tape.