The 5V49EE503NLGI is a clock generator and multiplexer from Renesas' VersaClock® III family. Its PLL can be bypassed, which means you get a clean reference path when the PLL's jitter isn't needed — useful for low-jitter fan-out or for feeding a downstream PLL that does its own cleanup. The PLL itself synthesizes up to 200 MHz from a crystal or LVCMOS input, and the 2:5 input-to-output ratio lets you route one of two input sources to five output banks.
200 MHz ceiling and 3.3V rail tolerance
The 200 MHz maximum output frequency covers most FPGA reference clocks, Ethernet PHY MACs, and SoC core clocks. The supply range is 3.135V to 3.465V — that's a 3.3V nominal rail with ±5% tolerance. If your board's 3.3V regulator holds within that band, no extra LDO is needed. The outputs are LVCMOS / LVTTL, so they drive standard digital loads without level translation.
Renesas lists the 5V49EE503NLGI as Active. The part ships in a tray, surface-mount in a 24-VFQFN exposed pad package with a 4x4 mm body. ROHS3 compliant.