200 MHz LVCMOS fanout buffer for industrial clock trees
The Renesas 5PB1102PGGI is a single-channel, 1:2 fanout buffer designed to distribute LVCMOS clock signals up to 200 MHz. It accepts a single LVCMOS input and provides two identical LVCMOS outputs with minimal skew, making it a straightforward choice for splitting a reference clock to multiple loads—FPGA banks, Ethernet PHYs, or ADC sampling clocks—without adding differential conversion overhead. The supply voltage spans 1.71V to 3.465V, covering 1.8V, 2.5V, and 3.3V logic rails directly.
The 5PB1102PGGI is a single-ended, non-differential buffer (No/No for differential input and output). That is the key distinction from differential fanout buffers like the 8SLVP1104ANLGI, which handles LVPECL, LVDS, or CML signals at up to 2 GHz. If your design uses differential signalling—common in high-speed SERDES or RF paths—this part will not drive those lines directly. For standard LVCMOS clock distribution at 200 MHz or below, it is a clean, low-skew fit.
The part is ROHS3 compliant.
8-TSSOP footprint and layout notes
Housed in an 8-TSSOP package (4.40 mm width, 0.173" pitch), the 5PB1102PGGI occupies minimal board area. Surface-mount assembly is standard; no exposed thermal pad, so standard reflow profiles for TSSOP-8 apply. Place the decoupling capacitor close to the supply pin—within 2 mm—to keep the clock jitter within the datasheet limits. The 1:2 ratio means the input trace sees only one load, simplifying impedance matching.