Timing-tree fit for 350 MHz differential clocks
The 5P49V6913A000NLGI is a VersaClock® 6 clock generator from Renesas, producing up to three output clocks from two input references. Its 350 MHz maximum output frequency and differential signaling on both sides (HCSL, LVDS, LVPECL) place it squarely in high-speed serial-interface timing trees — PCIe reference clocks, 10GbE MAC/PHY, or FPGA transceiver banks that need a clean, low-jitter source.
PLL architecture and fanout planning
The internal PLL supports a bypass mode, letting you feed a clean external clock straight through when the PLL is not needed — useful for test modes or when the system clock is already clean enough. The 2:3 input-to-output ratio means two reference inputs feed three clock outputs; the third output is synthesized from one of the inputs via the PLL, so you can generate a new frequency without adding a second oscillator. All three outputs support HCSL, LVCMOS, LVDS, and LVPECL levels, so the same device can drive a PCIe reference (HCSL), a SerDes PLL (CML-equivalent via AC-coupling), and a logic-level clock (LVCMOS) from one package.
Active lifecycle and compliance posture
Renesas lists the 5P49V6913A000NLGI as Active and ROHS3 compliant.