PLL-based clock generator for multi-protocol systems
The Renesas 5P49V5901B616NLGI8 is a VersaClock 5 programmable clock generator with an integrated PLL, designed to synthesize multiple output frequencies from a single reference. It accepts HCSL, LVCMOS, LVDS, LVPECL, or crystal inputs and delivers the same signal types on its four outputs. Two frequency maximums are specified: 200 MHz and 350 MHz. The 350 MHz tier covers high-speed serial interfaces like PCIe Gen3 or 10G Ethernet; the 200 MHz tier suits lower-rate LVCMOS clock trees. The PLL, combined with the divider block, allows integer-N or fractional-N multiplication from the input reference. Package is a 24-VFQFPN (4x4 mm) with exposed pad, surface-mount.
ROHS3 compliant. No special handling or exemption paperwork is needed for EU or California market shipments.
What the dual frequency maximum means for your board
The 350 MHz ceiling applies to differential outputs; the 200 MHz ceiling applies to LVCMOS outputs.