350 MHz PLL clock generator with 2:4 fanout
The 5P49V5901B000NLGI8 is a VersaClock® 5 clock generator from Renesas, built around a PLL core that synthesizes output clocks up to 350 MHz from any of four input references — HCSL, LVCMOS, LVDS, LVPECL, or a crystal. With a 2:4 input-to-output ratio and differential outputs on all four channels, this part fans out two reference clocks to four independent, phase-aligned copies — enough to drive multiple SerDes transceivers, FPGAs, or Ethernet PHYs from a single PLL bank.
I/O standards and signal integrity
Both the input and output stages support HCSL, LVDS, LVPECL, and LVCMOS — the four most common clock signaling formats in communications and computing. This means the same part can receive a 100 MHz LVDS reference from an FPGA and fan out 156.25 MHz HCSL clocks to a 10G Ethernet PHY without external translators. Because the differential input-to-output path is fully differential (Yes/Yes per the spec), the PLL preserves the low-jitter characteristics of the reference — critical when the output clock is used as a SerDes reference clock where phase noise directly impacts bit-error rate.
RoHS3 compliant (2015/863/EU) with no exemptions — the part is fully lead-free and compatible with standard Pb-free reflow profiles (260°C peak).