Clock multiplexer for redundant clock trees
The Renesas 552-02SCMGI is a 2:8 clock multiplexer that selects one of two LVCMOS input clocks and distributes it to eight LVCMOS outputs. It handles clock rates up to 200 MHz, making it a fit for FPGA reference-clock fanout, base-station timing cards, and industrial controller backplanes where a redundant oscillator or PLL source must be switched without glitching the downstream logic. Packaged in a 16-QFN measuring 2.5 mm × 2.5 mm, it fits tight layout budgets on multi-layer PCBs where clock traces need short, matched routes to the fan-out targets.
What the 200 MHz ceiling means for your clock tree
The 2:8 ratio means two input clock sources (e.g., primary and backup oscillators) feed the mux, and the selected clock appears on all eight outputs. That is enough fanout for a small FPGA bank plus a few PHYs or converters without adding a separate buffer stage. LVCMOS I/O on both sides keeps the signal swing compatible with standard logic families. No level translation needed when the upstream clock source and downstream loads are both LVCMOS.