1:5 clock fanout with 133.33 MHz ceiling
The 2305NZ-1HDCGI: The 1:5 ratio means a single clock source can drive five downstream loads — a common need when splitting a reference clock to multiple PLLs, FPGAs, or transceivers on the same board. Both input and output are non-differential LVCMOS, so this buffer is designed for single-ended clock trees.
Industrial temperature and package fit
The supplier device package is listed as 8-SOIC, which matches standard SOIC-8 land patterns — no exotic pad geometry to account for during PCB layout.