NXP Kinetis K10 series MK10DX256VMC7, 32-bit ARM Cortex-M4 MCU, 72MHz, 256KB Flash, 64KB SRAM, 2KB EEPROM, 74 I/O, 39x16-bit ADC, 1x12-bit DAC, CAN/EBI/I²C/SPI/UART, 121-MAPBGA (8x8 mm), -40°C to 105°C.
| Parameter | Value |
|---|---|
| Series | Kinetis K10 |
| Mounting | Surface Mount |
| Oscillator type | Internal |
| Program memory type | FLASH |
| Voltage - supply (Vcc (Vdd)) | 1.71V ~ 3.6V |
| Operating temperature | -40°C ~ 105°C (TA) |
| Speed | 72MHz |
| Package | Tray |
| RAM size | 64K x 8 |
| Core size | 32-Bit Single-Core |
| EEPROM size | 2K x 8 |
| Peripherals | DMA, I²S, LVD, POR, PWM, WDT |
| Connectivity | CANbus, EBI/EMI, I²C, IrDA, SPI, UART/USART |
| Number of i (O) | 74 |
| Core processor | ARM® Cortex®-M4 |
| Case | 121-LFBGA |
| Data converters | A/D 39x16b; D/A 1x12b |
| Program memory size | 256KB (256K x 8) |
The 64 KB SRAM leaves room for multiple packet buffers and a small heap without external RAM. The 2 KB EEPROM is useful for storing calibration constants, node IDs, or boot counters without wearing the Flash.
The 121-MAPBGA (8x8 mm) package is a fine-pitch BGA — expect a 4-layer or 6-layer PCB with microvias to route the inner balls. Reflow profile must match the solder-ball alloy;
The core runs at 72 MHz. At this clock rate, the Flash requires at least one wait state for zero-wait access; the Cortex-M4 pipeline handles it transparently, but firmware engineers should configure the Flash controller's wait-state register during clock initialization.
74 general-purpose I/O lines are available. The 121-ball BGA package dedicates the remaining balls to power, ground, and dedicated function pins (oscillator, analog reference, JTAG/SWD).
Within the Kinetis K10 family, pin-compatible variants differ by Flash and SRAM density — for example, the MK10DN512VMC7 offers 512 KB Flash. Package and pinout are identical across the 121-MAPBGA K10 options, so a BOM swap is possible if the memory budget changes, but no official cross-reference to a different series is recorded.