BFU520XRR

NXP Semiconductors

NXP Semiconductors BFU520XRR NPN RF transistor, 10.5 GHz transition frequency, 20 dB gain, 0.65 dB noise figure at 900 MHz, AEC-Q101 automotive qualified, SOT-143R surface mount package.

NXP Semiconductors BFU520XRR
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MOQ 1 · Tape & Reel (TR); Cut Tape (CT) · RoHS · EIA-481 · DAP/DDP · T/T

Technical specifications

BFU520XRR specifications
Parameter / AttributeSpecification / Value
MountingSurface Mount
FET typeNPN
Voltage - collector emitter breakdown12V
Current - collector (Ic)30mA
DC current gain (hFE) (Min) @ ic, vce60 @ 5mA, 8V
Power - max450mW
Frequency - transition10.5GHz
Operating temperature-40°C ~ 150°C (TJ)
Gain20dB
GradeAutomotive
PackageTape & Reel (TR); Cut Tape (CT)
QualificationAEC-Q101
CaseSOT-143R
Noise figure (dB typ @ f)0.65dB @ 900MHz

Technical details

RF performance for LNA and driver stages

The BFU520XRR is an NPN RF transistor from NXP, designed for low-noise amplification up to the low-GHz range. Its 10.5 GHz transition frequency and 20 dB gain make it suitable for LNA, driver, and buffer stages in automotive RF systems like tire-pressure monitoring, keyless entry, and telematics modules. The noise figure of 0.65 dB at 900 MHz is the figure of merit for front-end sensitivity — every tenth of a dB directly impacts the receiver's cascaded noise floor. For a 900 MHz ISM-band receiver, this transistor keeps the system NF below 1 dB with proper input matching.

Automotive-grade reliability and thermal envelope

Qualified to AEC-Q101, the BFU520XRR meets the stress, lifetime, and production-control requirements for automotive electronics. Maximum collector current is 30 mA with a collector-emitter breakdown of 12 V. These are the absolute-maximum ratings, not the bias point — the nominal operating region sits well below these limits. The 450 mW power dissipation in the SOT-143R package sets the thermal budget; for a typical LNA biased at 5 V and 10 mA, the 50 mW dissipation leaves ample margin.

SOT-143R footprint and board integration

The SOT-143R package is a four-lead surface-mount footprint with a collector pad that doubles as the thermal path. The PCB layout should follow the recommended land pattern in the NXP application note — the emitter leads are on opposite sides of the package, which simplifies the RF ground via placement for a common-emitter stage.

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