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NXP USA Inc. MKL28Z512VLL7 — Microcontrollers & Processors (MCU / MPU / DSP)

NXP MKL28Z512VLL7 Kinetis KL2 MCU, ARM Cortex-M0+, 72 MHz, 512 KB Flash

MPNMKL28Z512VLL7
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NXP Kinetis KL2 series, 32-bit ARM Cortex-M0+ MCU, MKL28Z512VLL7, 72 MHz, 512 KB Flash, 128 KB RAM, USB, FlexIO, 100-LQFP, -40 to 105°C.

$9.3396Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

MKL28Z512VLL7 specifications
ParameterValue
SeriesKinetis KL2
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))1.71V ~ 3.6V
Operating temperature-40°C~105°C(TA)
Speed72MHz
PackageTray
RAM size128K x 8
Core size32-Bit Single-Core
PeripheralsDMA, I²S, PWM, WDT
ConnectivityI²C, FlexIO, SPI, UART/USART, USB
Number of i (O)82
Core processorARM® Cortex®-M0+
Case100-LQFP
Data convertersA/D 24x16b; D/A 1x12b
Program memory size512KB (512K x 8)

Product details

The NXP MKL28Z512VLL7 is a 32-bit ARM Cortex-M0+ microcontroller from the Kinetis KL2 series, running at 72 MHz with 512 KB of Flash and 128 KB of RAM. The supply voltage range is 1.71 V to 3.6 V, and the operating temperature range is -40°C to 105°C.

72 MHz Cortex-M0+ — what that means on the bench

72 MHz is the top speed for this Cortex-M0+ core. The 512 KB Flash and 128 KB RAM support a bootloader plus application code. The MKL28Z512VLL7 adds FlexIO and 82 I/O pins.

The FlexIO block can emulate UART, SPI, I²C, or a custom parallel bus with programmable timing.

Frequently asked questions

What is the supply voltage of MKL28Z512VLL7?

The supply voltage range is 1.71 V to 3.6 V, which covers single-cell lithium and standard 3.3 V rails.

Can I replace MKL28Z512VLL7 with MKL27Z512?

The MKL27Z512 is a pin-compatible alternative in the same Kinetis KL2 family, but it lacks FlexIO and has a different peripheral set — check your firmware's register map before swapping.

What is MKL28Z512VLL7's core speed?

The core runs at 72 MHz, which is the top speed for this Cortex-M0+ implementation.