The 60 MHz core speed is the ARM7 synchronous maximum; at that clock the SRAM delivers single-cycle access for the vector table and critical ISR stacks. The 128 KB Flash holds a moderate application — a USB CDC class driver plus a sensor-fusion loop fits; a full TCP/IP stack with a web server will push against the limit. Internal oscillator is available; 45 GPIOs in 64-LQFP package.
Package is 64-LQFP (10x10 mm).
NRND — not for new designs
NRND status. Sourced to order; RFQ for availability.
