PLL-based jitter cleaning for high-speed clocks
The ZL30256LFG7 is a PLL-based jitter attenuator from Microchip, designed to clean up noisy clock sources in high-speed digital systems. It accepts a single-ended CMOS input and can produce up to 18 outputs in any mix of CMOS, HCSL, HSTL, LVDS, or LVPECL standards — covering the common logic families used on a typical FPGA or SerDes reference clock tree. With a maximum output frequency of 1.045 GHz, this part handles 10G-class SerDes reference clocks and high-speed ADC/DAC sample clocks. The three independent PLL circuits let you clean multiple clock domains from a single device, reducing board space and BOM count compared to using separate attenuators per rail.
80-LGA package and board integration
The 1.71V–1.89V core supply and 3.135V–3.465V I/O supply rails are separate, so you can run the core at 1.8V while the outputs swing at 3.3V to match downstream logic levels. The differential input and output capability means it can accept and deliver LVDS or LVPECL signals directly, avoiding external level translators.