14-SOIC footprint and board-fit
The TC9400EOD comes in a 14-SOIC package (0.154" body width, 3.90 mm) — a standard footprint that routes cleanly on a two-layer board. The 1.27 mm pitch leaves room for a guard ring around the analog input traces, which matters when the converter is handling low-level signals near its ±0.05% linearity floor. Supplier device package is 14-SOIC, matching the JEDEC MS-012 variation. No exposed pad — thermal dissipation relies on the copper pour under the body and the adjacent vias to the ground plane.
What the 100 kHz and linearity specs mean for your signal chain
100 kHz maximum frequency sets the conversion ceiling — a 0–10 V input maps to a 0–100 kHz output pulse train. For a 12-bit effective resolution at 100 kHz, the gate time needs to be at least 10 ms; shorter gate times trade resolution for update rate. ±0.05% linearity (typical) means the deviation from an ideal V/F or F/V transfer function stays within 500 ppm of full scale. In a temperature-controlled environment the ±40 ppm/°C full-scale drift adds about 0.4% error over a 0–70 °C range — budget this into the system accuracy calculation. The device operates bidirectionally: voltage-to-frequency conversion on the input side, frequency-to-voltage on the output. This makes it a direct fit for isolated analog transmission over a single twisted pair — the frequency signal carries through an optocoupler or pulse transformer without the linearity penalty of an analog isolator.
ROHS3 compliant, so it passes the material declaration requirements for EU and most global markets without an exemption expiry concern. Supplied in tube (standard 14-SOIC tube quantity). For high-volume pick-and-place, confirm the tube-to-reel transfer or order the tape-and-reel suffix variant if Microchip offers one — the tube orientation may require a different feeder setup.