AEC-Q100 grade-1 and 125°C — the underhood gate
The MCP48FVB04-E/MQ carries AEC-Q100 qualification and a -40°C to 125°C operating range — this is the grade-1 temperature band, suitable for engine-bay and transmission-control modules that see sustained 105°C ambient with transient excursions to 125°C. A part rated only to 85°C would require derating or active cooling in that environment; this one does not.
Four independent 8-bit DACs on one die, each settling to within 1 LSB in 7.8 µs typical. That settling time defines the per-channel update rate — a 7.8 µs step means you can sequence all four channels at roughly 128 kHz without bus contention, assuming the SPI clock keeps up. The INL of ±0.4 LSB and DNL of ±0.05 LSB guarantee monotonicity across the full code range, which matters for closed-loop actuator trim where a non-monotonic step could cause a control reversal. The output is voltage-unbuffered — the DAC's R-2R ladder drives the output pin directly. This means the output impedance is code-dependent (roughly 10-20 kΩ typical), so the load impedance must be high enough that the voltage error from the divider stays below 1 LSB. A buffer op-amp on the output is standard practice when driving a low-impedance or capacitive load.
20-VQFN with exposed pad — board-level checklist
The supplier device package identifier is 20-VQFN (5x5), matching the 5x5 mm body size. SPI data interface — the device accepts standard SPI frames; the serial clock and data lines are shared across the four channels with a single chip-select line. Daisy-chaining multiple devices on the same bus is possible if the SPI master supports the protocol extension.