16-bit pipelined ADC with digital down-converter
The Microchip MCP37D31-80E/TE is a 16-bit pipelined ADC sampling at 80 MSPS, built for wideband signal chains that need on-chip decimation filtering and a digital down-converter (DDC). Its eight differential inputs feed through a MUX-S/H-MUX-ADC front end, letting a single converter core digitize multiple analog channels with a 1:1 S/H-to-ADC ratio. The 121-TFBGA package (8x8 mm) keeps the footprint compact for dense receiver or beamforming boards, but the 0.50 mm ball pitch demands a controlled-impedance layout and a clean break-out on a four-layer or better PCB.
Digital down-converter and decimation filters
The integrated DDC and decimation filters reduce the output data rate from the 80 MSPS raw sample stream to a lower rate that matches the signal bandwidth — this cuts the LVDS lane count and relaxes the FPGA or DSP capture logic. The data interface supports both LVDS (parallel) and SPI, giving the system architect a choice between high-speed streaming and register-based configuration for filter coefficients and gain settings.
Wide temperature range and supply rails
Both analog and digital supplies run from 1.2 V to 1.8 V — a single 1.8 V rail can power the core, with the 1.2 V low end suiting low-power baseband ASICs.
Sourcing and cross-reference note
The closest functional peer in Microchip's portfolio is the MCP3564T-E/NC — a 24-bit sigma-delta ADC with 153.6 kSPS sampling, SPI interface, and an internal PGA. It is not a pin-compatible drop-in: the MCP37D31 uses a pipelined architecture at 80 MSPS with a DDC, while the MCP3564 targets low-speed, high-resolution measurement. A board designed for the MCP37D31 cannot accept the MCP3564 without a full layout change.