Dual-core dsPIC33CH — the motor-control workhorse in a 28-pin SSOP
The Microchip DSPIC33CH128MP202-I/SS is a 16-bit dual-core MCU from the dsPIC33CH family, combining a 180/200 MHz master core with a dedicated 200 MHz slave core for real-time control loops. It packs 152 KB Flash and 20 KB RAM into a 28-SSOP package, with a full motor-control peripheral set including PWM, QEI, and a 12-bit A/D converter. This is a part designed for applications that need deterministic response — think dual-sensor field-oriented control on a brushless DC motor, or a digital power supply with interleaved phases. The dual-core architecture offloads the control algorithm to the slave core while the master handles communications and system management.
180/200 MHz — what the dual-core speed buys you in a control loop
The master core runs at 180 MHz and the slave at 200 MHz. That 200 MHz slave drives the PWM and ADC trigger, closing the current loop without jitter from interrupt latency on the master. The 152 KB Flash is split between master and slave; each core has its own program memory space, so the slave's control code does not compete with the master's protocol stack for bus access. The 20 KB RAM holds the shared data structures — torque reference, rotor position, fault flags — passed through the inter-core mailbox.
Motor control peripherals — PWM, QEI, and the 12-bit ADC array
The peripheral set includes Motor Control PWM, QEI (quadrature encoder interface), and a 23-channel 12-bit A/D converter plus four 12-bit D/A converters. The PWM module supports complementary outputs with dead-time insertion, fault input, and trigger-to-ADC synchronisation — all clocked from the slave core's 200 MHz timer. The 21 available I/O pins in the 28-SSOP package constrain the peripheral mix: you trade off a UART for extra PWM channels or encoder inputs.
The 28-SSOP package (0.209-inch body width, 5.30 mm) is a standard surface-mount footprint shared across the dsPIC33CH family.
Sourcing and availability — quoted to order
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