LVPECL output and frequency range
The DSC8122AI2-PROGRAMMABLE: The LVPECL signalling provides the low-jitter, high-slew-rate edge needed for clocking 10/25/40/100 GbE PHYs, PCIe reference clocks, and SerDes transceivers — the differential pair rejects common-mode noise on the PCB trace.
Frequency stability and supply flexibility
The disable current is low enough to leave the oscillator powered on the same rail as the downstream logic without a dedicated power switch.