MEMS XO with HCSL output for high-speed serial clocks
The DSC8104DI5: The HCSL (High-Speed Current Steering Logic) differential output is the standard reference clock for PCIe, Ethernet PHYs, and many FPGA SerDes blocks — it drives 50-ohm terminated lines directly without external level translation. The total frequency stability of ±10 ppm covers temperature, supply, and aging — tight enough for 1000BASE-T Ethernet and PCIe Gen 1/2/3 reference clock jitter budgets without an external VCXO.
Supply voltage tolerance and standby function simplify power design
The standby function (pin-controlled) drops the oscillator into a low-power state — useful for automotive modules that need to wake on a CAN or LIN message and conserve battery draw when the system is off. Maximum supply current is 42 mA at full output swing. In a typical 3.3 V system, that's about 140 mW — budget this into the power tree alongside the downstream clock receiver's termination power.
The blank (user-programmable) variant means the oscillator is shipped without a pre-programmed frequency — the factory-programmed version is ordered under the same base number with a specific frequency suffix. For the DSC8104DI5, the frequency is set at the factory; verify the programmed frequency against your BOM before committing.