Triple-output MEMS oscillator for timing-tree consolidation
The DSC613NI2A-0106T: It outputs three independent LVCMOS clock signals: 19.2 MHz, 24 MHz, and 32.768 kHz — a frequency plan that directly serves a common timing-tree architecture in networking, industrial, and IoT designs.
The 19.2 MHz output typically clocks the SoC or FPGA core, the 24 MHz output drives the USB or Ethernet PHY, and the 32.768 kHz output provides a real-time clock or sleep-mode reference. Consolidating these three frequencies into one device eliminates three separate crystal or oscillator line items, reducing PCB area and procurement complexity. Maximum supply current is 6.5 mA with all three outputs active.