Obsolete — sourcing through independent channels
The DSC6122CI2A-00AV: No stock-holding claim; each lot is verified for authenticity and traceability before shipment.
For a video clock receiver with a PLL bandwidth above 10 kHz, the phase noise difference is absorbed by the loop filter. The typical supply current is 3 mA, making it suitable for power-sensitive designs where a quartz oscillator plus a separate clock generator would draw 10 mA or more.
4-VDFN footprint and layout considerations
Decoupling should be a 0.1 µF X7R capacitor placed within 2 mm of pin 4 (VDD) with a short via to the ground plane — the CMOS output edge rate is fast enough that a 10 nH via inductance creates a 30 mV supply bounce at 74.25 MHz switching, which couples into the output jitter measurement.