The DSC6111JI3B-024.8060T: Active current draw is 3 mA typical, and the standby (power-down) mode drops to 1.5 µA typical — the disable current is low enough that a coin-cell-backed RTC can keep the oscillator off without draining the battery.
Frequency stability and deployment context
Frequency stability is ±20 ppm across the operating temperature range. For a 24.806 MHz clock, that translates to a maximum drift of about 496 Hz — tight enough for CAN, LIN, or general-purpose microcontroller clocks where the system PLL can absorb the jitter.